2024 - T3 - WS1 - Deployment of post-quantum cryptography

Collection 2024 - T3 - WS1 - Deployment of post-quantum cryptography

Organizer(s) Kahrobaei, Delaram ; Perret, Ludovic ; Smith, Benjamin ; Le Van Gong, Hubert
Date(s) 07/10/2024 - 11/10/2024
linked URL https://indico.math.cnrs.fr/event/5776/
16 17

PQC on Microchips: Processors, Secure Elements, and SoCs

By Markku-Juhani O. Saarinen

A perspective on Post-Quantum Cryptography (PQC) deployment from the viewpoint of computer architecture and hardware security. The impact of PQC on the Instruction Set Architectures such as RISC-V ISA and system-on-chip (SoC) design in general. What do PQC cryptographic accelerators look like? How hard is it to deal with side-channel attacks? What is expected to change in the testing and certification processes of secure elements, trusted platform modules (TPMs), and root-of-trust (RoT) units?

Information about the video

Citation data

  • DOI 10.57987/IHP.2024.T3.WS1.016
  • Cite this video Saarinen, Markku-Juhani O. (11/10/2024). PQC on Microchips: Processors, Secure Elements, and SoCs. IHP. Audiovisual resource. DOI: 10.57987/IHP.2024.T3.WS1.016
  • URL https://dx.doi.org/10.57987/IHP.2024.T3.WS1.016

Bibliography

  • M.-J. Saarinen, "Accelerating SLH-DSA by Two Orders of Magnitude with a Single Hash Unit." IACR CRYPTO 2024. https://eprint.iacr.org/2024/367
  • H. Cheng, J. Großschädl, B. Marshall, D. Page, M.-J. Saarinen, "SoK: Instruction Set Extensions for Cryptographers." Preprint, 2024. https://eprint.iacr.org/2024/1323
  • T. Szymkowiak, E. Isufi, M.-J. Saarinen, "Marian: An Open Source RISC-V Processor with Zvk Vector Cryptography Extensions." Poster Abstract in Proc. ACM CCS 2024. https://eprint.iacr.org/2024/1449

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