PQC on Microchips: Processors, Secure Elements, and SoCs
A perspective on Post-Quantum Cryptography (PQC) deployment from the viewpoint of computer architecture and hardware security. The impact of PQC on the Instruction Set Architectures such as RISC-V ISA and system-on-chip (SoC) design in general. What do PQC cryptographic accelerators look like? How hard is it to deal with side-channel attacks? What is expected to change in the testing and certification processes of secure elements, trusted platform modules (TPMs), and root-of-trust (RoT) units?