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Quantum computing hardware: cost of fault-tolerance

By Mazyar Mirrahimi

Appears in collection : CEMRACS 2025: Quantum Computing / CEMRACS 2025: Calcul quantique

The remarkable progress in control and readout of atomic and solid-state qubits has led to an accelerated race towards building a useful quantum computer. A portion of the recent developments deal with noisy quantum bits and aim at proving an advantage with respect to classical processors. However, in order to fully exploit the power of quantum physics in computation, developing fault-tolerant processors is unavoidable. In such a processor, quantum bits and logical gates are dynamically and continuously protected against noise by means of quantum error correction. While a theory of quantum error correction has existed and developed since mid 1990s, the first experiments are being currently investigated in the physics labs around the world. I will review the main approach pursued in this direction and state of progress towards error corrected qubits. I will also present some shortcut approaches that are pursued to reduce the significant hardware overhead of error correction.

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  • DOI 10.24350/CIRM.V.20375203
  • Cite this video Mirrahimi, Mazyar (15/07/2025). Quantum computing hardware: cost of fault-tolerance. CIRM. Audiovisual resource. DOI: 10.24350/CIRM.V.20375203
  • URL https://dx.doi.org/10.24350/CIRM.V.20375203

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